Lattice introduces their new MachXO Crossover PLD family

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Lattice introduces their new MachXO Crossover PLD family

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MachXO combines an optimized Look-Up Table (LUT) fabric with Lattice's Flash plus SRAM non-volatile technology, providing the high pin-to-pin performance and instant-on of CPLDs, together with the flexibility of FPGAs.

MachXO is the perfect low-cost fit for glue logic, bus bridging, bus interfacing, power-up and control logic. Change the way you look at programmable logic.

MachXO devices are suitable for the implementation of a wide array of functions, including bus bridging, interfacing, control logic, clock management, power and reset control, glue logic, memory control and ASIC and FPGA configuration. These applications are found in a wide variety of end-markets, including Automotive, Consumer, Communications, Computing, Industrial, Medical, Military and Networking.

• High Performance – 3.5ns Pin-to-Pin
• TransFR™ Technology Supports Simple Field Upgrades
• Sleep Mode Reduces Standby Power to <100µA
• Flexible LUT Architecture – 256 to 2280 LUTs
• Embedded and Distributed Memory
• Supports LVCMOS, LVTTL, PCI, LVDS
• Up to 2 Analog PLLs per Device
• IEEE 1149.1 Boundary Scan Test & Programming
• Supports Power Supplies from 1.2 to 3.3V

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